Wafer level packaging is gaining interest throughout the semiconductor industry due to advantages in cost and performance. When standard wafer level package technologies are used, all technology process steps are performed at the wafer level. Since standard wafer level packages are fan-in solutions, only a limited number of contact pads under the semiconductor chip is possible. Thus, for the placement of a large number of contact pads the semiconductor chip may be designed bigger or an additional material may be placed as a space holder around the die to bear the wiring that allows fan-out redistribution.
Wafer level packaging usually involves grinding steps to reduce the thickness of the semiconductor die. Any grinded semiconductor surface contains, however, a system of cracks, ridges and valleys. These damages in the semiconductor material may induce cracks through the semiconductor bulk material if additional mechanical stress is applied. Such mechanical stress may occur during processing, handling or shipment of the semiconductor devices or during the use in an application, such as a mobile phone.